Publisher's Synopsis
Excerpt from A Product Design Problem in Semiconductor Manufacturing
Because of the complexity of the technology and the fast-changing nature of the semi conductor industry, the yield of non-defective chips in wafer fabrication can be low and very erratic. Average yield rates can vary from several percent up to eighty or ninety percent depending upon the maturity and complexity of the product. Chips are made on wafers, and wafers are produced in lots, where the lot size is typically between five and fifty. In this paper, three different possibilities for producing defective chips will be explicitly considered: an entire lot can be defective, an entire wafer in a non-defective lot can be defective, and finally an individual chip on a non-defective wafer can be defective.
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