Verilog Coding for Logic Synthesis

Verilog Coding for Logic Synthesis

Hardback (13 May 2003)

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Publisher's Synopsis

Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses

Book information

ISBN: 9780471429760
Publisher: Wiley
Imprint: Wiley-Interscience
Pub date:
DEWEY: 621.395
DEWEY edition: 21
Language: English
Number of pages: 309
Weight: 588g
Height: 241mm
Width: 161mm
Spine width: 22mm